module SN74HC165#(
    parameter MSB = 8
)(
    input clk,              // Clock
    input serial_in,        // Serial Input
    input shift_load,       // Load
    input output_enable,    // output Enable
    
    input [MSB - 1 : 0] par_in, // Data Input
    output reg serial_out       // Data Output
);

    reg [MSB - 1 : 0] shift_reg;
    wire out_clk;
    
    assign out_clk =  output_enable & clk;
    
    always @(posedge out_clk or negedge shift_load) begin
        if(!shift_load) begin
            shift_reg <= par_in;
        end else begin
            shift_reg <= {shift_reg[6:0], serial_in};
            serial_out <= shift_reg[7];
        end
    end
    
    // assign serial_out = shift_reg[7];

endmodule






